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Researchers unveil experimental 36-core chip

2014-06-24 09:14 by
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A group led by Li-Shiuan Peh, the Singapore research professor of electrical engineering and computer science at MIT, has recently unveiled a 36-core chip that features just such a "network-on-chip."

By enabling data transfers between cores and cache in a more coherent manner, the chip reduces the number of cycles required to execute tasks. Until now ensuring that cores' locally stored copies of globally accessible data remain up to date has been a problem.

Each core in the chip is connected only to those immediately adjacent to it. This means that it is possible to reach the neighbouring chip really quickly and have multiple paths to your destination. So if you're going way across, rather than having one congested path, you could have multiple ones.

With the help of mini-routers, MIT researchers have devised a novel way to reroute data packets to free up bandwidth within multicore chips, Bhavya Daya, a Ph.D. candidate in MIT's Department of Electrical Engineering and Computer Science said. The research could benefit highly parallel applications such as financial analytics and particle simulation studies.

Read more -here-


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